At very high frequencies, each trace, each pin, is an RF emitter and receiver. Without a carefully designed layout, interference signals can easily obscure the signals that designers want to deal with. The design choice is first considered from the overall situation of the architecture and gradually refined to sub-millimeter-level traces. There are some practically tried and verified techniques that can help manage such a process.
This document describes the practical problems of real system design and how to minimize signal attenuation in RF environments.
What advanced technologies need to pay attention to to achieve higher signal processing performance?
PCB layout
Schematic
Key component positioning and signal routing
Power bypass
Parasitic effects, vias, and placement
Ground layer
High-speed circuit performance is closely related to circuit board layout
PCB layout is one of the last steps in the design process and often fails to receive enough attention. The performance of high-speed circuits is closely related to the layout of the circuit board. Here we will introduce some practical layout principles that will help:
Improve the layout process
Helps ensure the expected performance of the circuit
Reduce design time
Reduce design costs
Good layout based on excellent schematics
Schematic basic functions
Indicates the actual circuit connection
Generate NetList for layout
Can it be more efficient?
Can you express the function more clearly?
Others can understand the circuit
Can I display the signal path?
Assist layout
Assist troubleshooting and debugging
Representation function
Can it be more attractive?
Increased cognitive value
More effective schematics speed time-to-market
Does the example look better?
A more complicated circuit
Just like real estate, location is everything
Input/output and power connections on the circuit board are generally established
The location and signal routing of components need careful consideration and careful planning
The use of plies
Hollowing of the slab
Signal wiring
Loop routing
a better way
Use the GND and PWR layers to reduce the loops R and L.
Use separate AGND and DGND layers to minimize the digital coupling of the AGND plane.
Functional division
Group functionally related components.
Place the function with the signal path.
First, the functional layout along the signal path is through input and output.
Then realize the connection between the functions.
Example
Two inputs. Both ensure balance.
Gain and feedback. Both ensure symmetry.
Output. Both ensure symmetry.
Level conversion access signal path. Both ensure symmetry.
Accessibility features.
The key signal path is as short as possible.
The critical signal path uses an alternate path to maintain balance.
Packaging plays an important role in high-speed applications
Small package
Better high frequency response
Compact layout
Lower package parasitics
Low-distortion pinout (dedicated feedback)
Compact layout
Streaming signal flow
Lower distortion
PCB design
Typical 62mil (1.6mm) 6-layer PCB Stackup
Silk screen
Printed assembly and/or component ID information.
Only provide information. Does not affect performance. not necessary.
Information includes text, lines, shapes.
If the location of the information is not carefully considered, the information will be useless.
Minimum line width = 5 mils (0.127 mm)
The ratio of the height of the text to the width of the line should be greater than 12 so that the text is identifiable.
Do not place text on vias, holes, or bond pads.
Keep a minimum distance between bond pads.
The quality of the products varies from manufacturer to manufacturer, and sharp edges to dirty are possible.
Shield
Protect the copper sheet from the environment.
Minimize Solder Bridging A careful design prevents bridging.
Affect the PCB performance to a certain extent.
No need. It plays a key role in extending the life of the PCB. Greatly improve PCB assembly yield.
Usually green, some other popular colors are black, blue, red, white.
Copper sheet
It can be a signal layer or a slab layer.
It is usually a 1.4 mil (0.04 mm) thick copper plate. Can be thicker.
Etch to form signal traces and bond pads.
The minimum trace width is 4 mils (0.1 mm).
The minimum space requirement between two objects is 4 mils (0.1 mm).
Compose with other copper plates nearby.
With inductance.
PCB material selection example
Isola - FR4 type
Common materials.
High-temperature version of lead-free soldering
High dielectric constant: 4.7-4.2. Generates high parasitic capacitance
Rated at 1 GHz
Controlled impedance alignment is acceptable but not optimal
Rogers - PTFE type
Good high frequency, high temperature materials
Low dielectric constant. 2.2 and above. Reduces parasitic capacitance
high cost
Good impedance consistency
Rated at 10 GHz
Many other manufacturers. Some vendor performance specifications are similar to the above.
Component Bonding Pad Design
Bonding pad size
Usually 30% larger than component pads.
Can use soldering iron
Visual inspection of solder joints
Accepts components with large positioning errors
Increase Parasitic Capacitance - Reduce Effective Usable Frequency
Increase the possibility of solder bridging
Need more board space
Minimum size exceeds the standard: 0-5% larger than the component pad.
Maintain mechanical strength
The contact area between the component and the PCB remains unchanged
Reduce Parasitic Capacitance - Maintain More Usable Frequency
Reduce required board space
Pad shape
Usually rectangular with sharp corners
The fillet allows the pad to trace spacing to be tighter. Reduce board size.
Signal wiring
Use GND and PWR
Use “pad via†method to connect pad to layer to minimize parasitic effects
Place the functional module components as close as possible
0.5 mm device spacing is sufficient for manual placement
Minimize the number of vias in the signal trace. The less the better
Ensure that the traces in the same functional module are on the same layer.
Bypass capacitors
Keep the adjacent layers as close as possible
Avoid unnecessary vias penetrating the board.
Avoid hollowing the board
Keep straight as far as possible
Minimize steering and turning as much as possible
Example
Performance and PCB
Performance and component location
Crosstalk and coupling
Capacitive crosstalk or coupling
Due to parallel traces from above and below, parasitic capacitance results
The solution is to run vertically to reduce trace coupling and area
Inductive Crosstalk
Inductive crosstalk originates from the interaction of magnetic fields between long distances and lines
Inductive crosstalk falls into two categories: forward and reverse
Reverse crosstalk refers to the noise closest to the driver on the affected trace
Forward crosstalk refers to the noise furthest from the driver on the driven line
Minimize crosstalk by
Increase trace spacing (Improved isolation)
Use protective traces
Using differential signals
Bypass is necessary to ensure high-speed circuit performance
Place the capacitor at the power pin
Capacitor provides low impedance AC loop
Provides local charge storage space for fast rising/falling edges
Minimize the length of the trace
Close to the load circuit
Helps reduce transient currents in the ground plane
value
Single circuit performance
Keep AC impedance low
Multiple resonance
Ferrite beads
Optimized load and bypass capacitor placement and ground loops
Board capacitance
Power layer capacitance
Capacitance model
Capacitor selection
Multiple shunt capacitors
Parasitic effects can cause performance degradation and distortion
Trace/pad capacitance and inductance
Internal or bottom plate
A spacer capacitor is formed with a power plane underneath (not shown).
spacing
A longer distance eliminates the interaction with the controlled impedance layer above it.
Controlled impedance layer
The traces of the top signal layer and the distance between the layers form a transmission line with characteristic impedance.
Top (signal) layer
Traces are transmission lines with characteristic impedance
With signal traces and component bond pads.
Top welding shield
Can affect the characteristic impedance
Via parasitic effect
Via placement
0603 and 0402
Capacitive parasitic model
C = capacitance
RP = Insulation resistance
RS = Equivalent Series Resistance (ESR)
L = inductance of the pin and board
RDA = Dielectric Absorption
CDA = Dielectric Absorption
Resistance parasitic model
R = resistance
CP = Shunt Capacitor
L= Equivalent series inductance (ESL)
Low-frequency operational amplifier schematic
High Speed ​​Operational Amplifier Schematic
High-frequency operational amplifier schematic
Parasitic capacitance simulation schematic
The frequency response when the parasitic capacitance is 1.5pF
Inverting input 1pF with parasitic capacitance
1.5dB spike
Instability, oscillation
Parasitic inductance
Parasitic inductance simulation schematic
Impulse response with ground plane and no ground plane
Oscillations show the effect of traces with a 2.54 cm length on the non-inverting input of a high-speed op amp
Its equivalent inductance is about 29nH, enough to cause sustained low voltage oscillation
Ground and power planes
Ground and power planes provide
Common reference point
shield
Reduce noise
Reduces parasitic effects
Cooling
Power distribution
High value capacitor
Recommendations for ground planes and power planes
There is no 100% effective single grounding method!
Each PCB must have at least one layer dedicated to the ground plane!
Increase the ground plane as much as possible, especially under high operating frequency traces
Try to use a viable thick metal (reduce resistance, increase heat dissipation)
Use multiple vias to connect the same ground plane together
When starting to design the layout, set up dedicated layers for the analog and digital ground planes and separate only when necessary
Follow the recommendations of the mixed-signal device data sheet.
Keep bypass capacitors and load loops as close as possible to reduce distortion
Jumper options for analog and digital ground plane connections
to sum up
High-speed PCB design requires careful consideration and attention to detail
Provide as much information as possible on the schematic
The position of the component on the board is as important as the positioning of the entire circuit
Design the layout of the circuit board to be predictable, do not hesitate
Use Multiple Capacitors in Power Bypass
Must consider and handle parasitic effects
Ground and power planes play a key role in reducing noise and reducing parasitics
New packaging and pinouts help improve performance and increase layout compactness
There are several ways to choose the signal distribution, remember to choose the applicable method
Be careful when checking layout
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