Why is the Miller effect notorious in the MOS driver?

The gate driving process of the MOSFET can be simply understood as the charging and discharging process of the input capacitance of the driving source to the MOSFET (mainly the gate-source capacitance Cgs); when the Cgs reaches the threshold voltage, the MOSFET will enter the on state; when the MOSFET is turned on After that, Vds begins to fall, and Id starts to rise. At this time, the MOSFET enters the saturation region. However, due to the Miller effect, Vgs will not rise for a while, and Id has reached its maximum, and Vds continues to drop until Miller capacitance. Fully charged, Vgs rises again to the value of the drive voltage. At this point, the MOSFET enters the resistance region, and Vds is completely lowered and the turn-on is completed.

Since the Miller capacitor prevents the rise of Vgs, thus preventing the Vds from falling, this will lengthen the loss. (Wgs rises, the on-resistance decreases, and Vds decreases)

The Miller effect is notorious in the MOS driver. It is the Miller effect caused by the Miller capacitance of the MOS tube. During the turn-on of the MOS transistor, the GS voltage has a stable value after the GS voltage rises to a certain voltage value. The voltage begins to rise again until it is fully turned on. Why is there a steady value for this? Because, before the MOS is turned on, the D-pole voltage is greater than the G-pole voltage, and the MOS parasitic capacitance Cgd needs to be charged to the G-pole and neutralize the charge when it is turned on. Since the MOS is fully turned on, the G-pole voltage is greater than the D-pole. Voltage. The Miller effect can seriously increase the turn-on loss of MOS. (The MOS tube cannot enter the switch state very quickly)

So there is the so-called totem drive! ! When MOS is selected, the smaller the Cgd is, the smaller the turn-on loss is. The Miller effect cannot disappear completely.

The Miller platform in a MOSFET is actually a typical sign that the MOSFET is in the "amplifier region."

Using an oscilloscope to measure the GS voltage, you can see that there is a platform or pit during the voltage rise, which is the Miller platform.

The Miller effect means that the Miller platform is generated during the opening of the MOS tube. The principle is as follows.

Theoretically, the driver circuit adds a large enough capacitance between the G and S stages to eliminate the Miller effect. But at this time, the switching time will drag a long time. It is advantageous to add a capacitor value of 0.1Ciess to the recommended value.

The flat part of the thick black line in the picture below is the Miller platform.

The plot of the pruning factor is at the first turning point: Vds begins to conduct. The change in Vds forms a differential by the internal resistance of Cgd and the drive source. Since Vds is approximately linearly decreasing, the linear differentiation is a constant, resulting in a platform at Vgs.

The Miller platform is caused by the capacitance across the gd of mos, which is Crss in the mos datasheet.

This process is to charge Cgd, so the Vgs change is very small, when the Cgd is charged to the Vgs level, Vgs will continue to rise.

When mos is just turned on, it is quickly discharged by mos, and then reversely charged by the driving voltage, sharing the driving current, so that the voltage rise on Cgs becomes slow and the platform appears.

T0~t1: Vgs from 0 to Vth.Mosfet does not pass. Current is parasitic diode Df.

T1~t2: Vgs from Vth to Va. Id

T2~t3: Vds drop. Causes the current to continue to pass Cgd. The higher the Vdd, the longer it takes.

Ig is the drive current.

Start falling faster. When Vdg is close to zero, Cgd increases. Until Vdg becomes negative, Cgd increases to the maximum. The decline slows down.

T3~t4: Mosfet is fully turned on and runs in the resistor region. Vgs continues to rise to Vgg.

At the end of the platform, VGS continues to increase, and IDS is very small. That is because MOS is saturated. . . However, from the map of the landlord, this platform still has a length.

During this platform, it can be considered that MOS is in the amplification period.

Before the previous inflection point: MOS deadline, when Cgs is charged, Vgs is forced to Vth.

The previous inflection point: MOS officially entered the enlargement period

At the next inflection point: MOS officially exits the amplification period and begins to enter the saturation period.

When a voltage V with a slope of dt is applied to capacitor C (such as the output voltage of the driver), the current in the capacitor will increase:

I=C×dV/dt (1)

Therefore, when a voltage is applied to the MOSFET, an input current Igate = I1 + I2 is generated, as shown in the following figure.

Using equation (1) on the right voltage node, you can get:

I1=Cgd×d(Vgs-Vds)/dt=Cgd×(dVgs/dt-dVds/dt) (2)

I2=Cgs×d(Vgs/dt) (3)

If the gate-source voltage Vgs is applied to the MOSFET, its drain-source voltage Vds will drop (even if it falls nonlinearly). Therefore, the negative gain connecting the two voltages can be defined as:

Av=- Vds/Vgs (4)

Substituting equation (4) into equation (2), you can get:

I1=Cgd×(1+Av)dVgs/dt (5)

During conversion (on or off), the total equivalent capacitance Ceq of the gate-source is:

Igate=I1+I2=(Cgd×(1+Av)+Cgs)×dVgs/dt=Ceq×dVgs/dt (6)

The term (1+Av) is called the Miller effect, which describes the capacitive feedback between the output and the input in an electronic device. When the gate-drain voltage is close to zero, the Miller effect will occur.

The most powerful phase of Cds shunting is in the magnified area. Why? Because this stage Vd changes the most. The platform is formed at this stage. You can think that the gate current Igate is completely absorbed by Cds and no current flows to Cgs.

Note the representation in the data sheet

Ciss=Cgs+Cgd

Coss=Cds+Cgd

Crss=Cgd