1 Introduction
LED video display has high brightness, wide viewing angle, long life, high cost performance, and can display various texts, graphics and images simultaneously with the computer. It can play TV, video, video and other video signals in real time, and can input and edit each time. The advantages of multimedia data make it widely used in many public places on the street, in commercial centers, sports venues, entertainment venues and control centers. However, due to technical problems, the large video display also faces severe challenges, mainly in the low gray level, serious loss of brightness, and low refresh rate. In addition, the video signal source of this paper comes from the DVI (DigitalVideo InteRFace) interface. The DVI interface outputs a digital video signal. The amount of information is large. Generally, it is buffered by an external RAM (Random Array Memory), and then the video signal is processed by the processor. There are many types of external memories that can be used for digital image storage, such as SRAM, DRAM, and SDRAM, which vary in capacity and speed. DRAM and SDRAM are dynamic memories, which have large capacity and need to be refreshed during use. When the processor does not have an external dynamic RAM interface, it is necessary to design a refresh circuit, which brings inconvenience to the system application; SRAM does not need to be refreshed, no dedicated interface is required, and real-time performance is required. Ok, and hop address addressing is possible, so this article uses SRAM as the external cache memory. The split-area storage technology is adopted to greatly improve the refresh frequency, and the image display effect is clear and stable, and a video display system with a resolution of 800×256, a refresh frequency of 90 Hz, and a red, green and blue color of 256×256×256 gray levels is realized. At the same time, with this technology, the brightness and gray level are easily adjustable, and the brightness loss is corrected.
2 system components
The overall block diagram of the LED video display system is shown in Figure 1: The system consists of two parts: transmit and receive. The function of the transmit part is mainly to encode and decode the video signal transmitted by the DVI interface to form 24b true color video data and dot clock (CLK). The control signals such as the line sync signal (HS), the field sync signal (VS), and the data valid signal (DE) are transmitted to the receiving card through the LVDS (LowVoltage Differential Signaling) level, and are transmitted to the specific drive through the data processing of the receiving card. Structure (1/8 scanning mode, 74HC595 driver chip) rhyme LED large screen. The focus of this article is to introduce the data processing module of the receiving card.
3 data processing
The data processing flow is shown in Figure 2: the receiving card receives the video signal (control signal and data signal) transmitted from the transmitting card, and separates the data in the video signal through the bit plane, stores it in the external buffer, and then reads the partition. Transfer to the display driver screen. The plane separation module recombines the same weights of different data into new data and stores them in the memory. The external cache uses two SRAM ping-pong buffering techniques to implement pipeline processing of data. The principles and implementations of the plane separation module and the partition partition storage are described below.
3.1 plane separation module
The gray level control mode adopted by the video display screen is a combination of field superposition and duty ratio, as shown in Table 1: where the field superposition is to achieve different gray levels by constant frequency scanning of different fields, such as D7 to D4 of Table 1; duty ratio control refers to controlling the duty ratio of the lighting time and the off time to realize the adjustment of the gradation, as shown in D1 to D0 of Table 1. The premise of these two methods is to achieve the plane separation of video data. The bit plane separation is implemented by FPGA, which includes two modules, a data shift register and a data selector. The block diagram realized by VHDL is shown in Fig. 3. Among them, r0-7, g0-7, and b0-7 are respectively red, green, and blue colors of true color image data, occupying one byte respectively. The 24-bit data lines are respectively registered in an 8-bit wide data shift register and then output to an external buffer through a color bit selector. The bit plane separation is realized by controlling the address of the buffer, and the data width of the external buffer is 24 bits, so that the three colors of RGB are separated in parallel. The shift register uses the pipeline technology to shift the same weight of the ninth data while latching the same weight of the first 8 data, thus improving the efficiency of data processing.
3.2 Partitioned partition storage
After the data is separated by the bit plane, the same weight of different data constitutes new data. By controlling the address of the memory, the same weight of all the data of one frame is written in the same segment of the memory, so the requirement for the write address generator is relatively high. . The system requires 256 levels of gray, then the memory is divided into 8 segments, each segment storing bits (fields) representing the same weight. Among them, 8 segments are replaced by 3 (23) address lines, and the large screen with resolution of 800*256 has 256 rows and 800 columns, then the row address is represented by 8 (28) address lines, which are 8 address lines. The first 5 bits are the area address (32 areas), and the last 3 bits are the row address of one area (1/8 scan). The column address is represented by 7 (27) address lines. Because the memory is 24 bits wide, one memory cell represents the same weight of the 8 RGB points of the LED display. The order of priority from high to low is: field address column address. Row address. The counters are respectively implemented by the counters, and the three counters are cascaded to form the write address of the memory, and the connection manners are: field address (A17 to A15), area address (A14 to A10), and area address (A9 to A7). Column address (A6 to A0). It can be seen that the field (eight fields) storage can be achieved by changing the priority of the memory address lines.
The data is written into the memory in 8 fields, and is read out in 19 fields, and the display time of each field is controlled. Therefore, when generating the field address counter of the read address, first design a 19-digit counter counter19 (0 to 18). Table 2 shows the relationship between counter19 and the field address counter: the display time of each field is realized by a comparator, and the gray level and the brightness can be flexibly corrected by changing the value in the comparator.
The LED display requires 32 zones to be lit at the same time, using parallel processing of data to reduce hardware consumption and system operating frequency. Increase the refresh rate. Since the memory can only read one data at a time, it is necessary to use a partition latch and then output the 32-region data in parallel.
The row address and column address are the same as the write address generator principle. Here is a brief introduction to their priority. The data is already separated from the plane, so to achieve simultaneous display of 32-zone data, the priority of the zone address should be the highest, followed by the column address, then the row address, and finally the field address. The connection to the memory is the same as the write address.
4 simulation waveform
The simulation waveform of the plane separation module is shown in Figure 4: RGBdin[23..16] is the upper eight bits of the input data, and rgb_regroup_output[23..16] is the upper eight bits of the output data. Flag is the input data valid signal flag, and flag_d el ay85 is the flag for outputting the valid signal.
The waveform analysis is as follows:
The first 7 data of the first 8 data inputs are 00h, and the 8th is 02h. The output of these 8 data is separated from the table. See Table 3. It can be seen from Table 3 that the first 8 data turns are realized. Read it from right to left.
Figure 5 shows the simulated waveform of the write address. It can be seen that the field address has the highest priority. When the field address is 7h, the column address is incremented by 1. When the column address is 63h, the row address is incremented by 1. When the row address is 7h, the area address is plus 1. Similarly, it can be seen that the carry sequence of the read address of Figure 6 is: when the area address is 1Fh, the column address is incremented by 1, the column address is 63h, the row address is incremented by 1, and the row address is 7h, the field address is counted according to the 19-field principle. . When the row address in Figure 6 is 7h, the field address is not incremented by 1. Figure 7 shows the duty cycle signal controlled by the field address counter. The signal is connected to the enable end of the display driver board line drawing signal, and the display time is controlled by controlling the scan signal, thereby realizing the gray level.
5 Conclusion
Aiming at the refresh rate and gray scale control problems encountered by the system of LED video display, this paper proposes a sub-area partition storage technology, and introduces its principle and implementation in detail. Through waveform simulation and engineering application, this method can well solve the problem of image flicker and large brightness loss in LED display control system, and its gray level and brightness control can be flexibly corrected.
LED video display has high brightness, wide viewing angle, long life, high cost performance, and can display various texts, graphics and images simultaneously with the computer. It can play TV, video, video and other video signals in real time, and can input and edit each time. The advantages of multimedia data make it widely used in many public places on the street, in commercial centers, sports venues, entertainment venues and control centers. However, due to technical problems, the large video display also faces severe challenges, mainly in the low gray level, serious loss of brightness, and low refresh rate. In addition, the video signal source of this paper comes from the DVI (DigitalVideo InteRFace) interface. The DVI interface outputs a digital video signal. The amount of information is large. Generally, it is buffered by an external RAM (Random Array Memory), and then the video signal is processed by the processor. There are many types of external memories that can be used for digital image storage, such as SRAM, DRAM, and SDRAM, which vary in capacity and speed. DRAM and SDRAM are dynamic memories, which have large capacity and need to be refreshed during use. When the processor does not have an external dynamic RAM interface, it is necessary to design a refresh circuit, which brings inconvenience to the system application; SRAM does not need to be refreshed, no dedicated interface is required, and real-time performance is required. Ok, and hop address addressing is possible, so this article uses SRAM as the external cache memory. The split-area storage technology is adopted to greatly improve the refresh frequency, and the image display effect is clear and stable, and a video display system with a resolution of 800×256, a refresh frequency of 90 Hz, and a red, green and blue color of 256×256×256 gray levels is realized. At the same time, with this technology, the brightness and gray level are easily adjustable, and the brightness loss is corrected.
2 system components
The overall block diagram of the LED video display system is shown in Figure 1: The system consists of two parts: transmit and receive. The function of the transmit part is mainly to encode and decode the video signal transmitted by the DVI interface to form 24b true color video data and dot clock (CLK). The control signals such as the line sync signal (HS), the field sync signal (VS), and the data valid signal (DE) are transmitted to the receiving card through the LVDS (LowVoltage Differential Signaling) level, and are transmitted to the specific drive through the data processing of the receiving card. Structure (1/8 scanning mode, 74HC595 driver chip) rhyme LED large screen. The focus of this article is to introduce the data processing module of the receiving card.
3 data processing
The data processing flow is shown in Figure 2: the receiving card receives the video signal (control signal and data signal) transmitted from the transmitting card, and separates the data in the video signal through the bit plane, stores it in the external buffer, and then reads the partition. Transfer to the display driver screen. The plane separation module recombines the same weights of different data into new data and stores them in the memory. The external cache uses two SRAM ping-pong buffering techniques to implement pipeline processing of data. The principles and implementations of the plane separation module and the partition partition storage are described below.
3.1 plane separation module
The gray level control mode adopted by the video display screen is a combination of field superposition and duty ratio, as shown in Table 1: where the field superposition is to achieve different gray levels by constant frequency scanning of different fields, such as D7 to D4 of Table 1; duty ratio control refers to controlling the duty ratio of the lighting time and the off time to realize the adjustment of the gradation, as shown in D1 to D0 of Table 1. The premise of these two methods is to achieve the plane separation of video data. The bit plane separation is implemented by FPGA, which includes two modules, a data shift register and a data selector. The block diagram realized by VHDL is shown in Fig. 3. Among them, r0-7, g0-7, and b0-7 are respectively red, green, and blue colors of true color image data, occupying one byte respectively. The 24-bit data lines are respectively registered in an 8-bit wide data shift register and then output to an external buffer through a color bit selector. The bit plane separation is realized by controlling the address of the buffer, and the data width of the external buffer is 24 bits, so that the three colors of RGB are separated in parallel. The shift register uses the pipeline technology to shift the same weight of the ninth data while latching the same weight of the first 8 data, thus improving the efficiency of data processing.
3.2 Partitioned partition storage
After the data is separated by the bit plane, the same weight of different data constitutes new data. By controlling the address of the memory, the same weight of all the data of one frame is written in the same segment of the memory, so the requirement for the write address generator is relatively high. . The system requires 256 levels of gray, then the memory is divided into 8 segments, each segment storing bits (fields) representing the same weight. Among them, 8 segments are replaced by 3 (23) address lines, and the large screen with resolution of 800*256 has 256 rows and 800 columns, then the row address is represented by 8 (28) address lines, which are 8 address lines. The first 5 bits are the area address (32 areas), and the last 3 bits are the row address of one area (1/8 scan). The column address is represented by 7 (27) address lines. Because the memory is 24 bits wide, one memory cell represents the same weight of the 8 RGB points of the LED display. The order of priority from high to low is: field address column address. Row address. The counters are respectively implemented by the counters, and the three counters are cascaded to form the write address of the memory, and the connection manners are: field address (A17 to A15), area address (A14 to A10), and area address (A9 to A7). Column address (A6 to A0). It can be seen that the field (eight fields) storage can be achieved by changing the priority of the memory address lines.
The data is written into the memory in 8 fields, and is read out in 19 fields, and the display time of each field is controlled. Therefore, when generating the field address counter of the read address, first design a 19-digit counter counter19 (0 to 18). Table 2 shows the relationship between counter19 and the field address counter: the display time of each field is realized by a comparator, and the gray level and the brightness can be flexibly corrected by changing the value in the comparator.
The LED display requires 32 zones to be lit at the same time, using parallel processing of data to reduce hardware consumption and system operating frequency. Increase the refresh rate. Since the memory can only read one data at a time, it is necessary to use a partition latch and then output the 32-region data in parallel.
The row address and column address are the same as the write address generator principle. Here is a brief introduction to their priority. The data is already separated from the plane, so to achieve simultaneous display of 32-zone data, the priority of the zone address should be the highest, followed by the column address, then the row address, and finally the field address. The connection to the memory is the same as the write address.
4 simulation waveform
The simulation waveform of the plane separation module is shown in Figure 4: RGBdin[23..16] is the upper eight bits of the input data, and rgb_regroup_output[23..16] is the upper eight bits of the output data. Flag is the input data valid signal flag, and flag_d el ay85 is the flag for outputting the valid signal.
The waveform analysis is as follows:
The first 7 data of the first 8 data inputs are 00h, and the 8th is 02h. The output of these 8 data is separated from the table. See Table 3. It can be seen from Table 3 that the first 8 data turns are realized. Read it from right to left.
Figure 5 shows the simulated waveform of the write address. It can be seen that the field address has the highest priority. When the field address is 7h, the column address is incremented by 1. When the column address is 63h, the row address is incremented by 1. When the row address is 7h, the area address is plus 1. Similarly, it can be seen that the carry sequence of the read address of Figure 6 is: when the area address is 1Fh, the column address is incremented by 1, the column address is 63h, the row address is incremented by 1, and the row address is 7h, the field address is counted according to the 19-field principle. . When the row address in Figure 6 is 7h, the field address is not incremented by 1. Figure 7 shows the duty cycle signal controlled by the field address counter. The signal is connected to the enable end of the display driver board line drawing signal, and the display time is controlled by controlling the scan signal, thereby realizing the gray level.
5 Conclusion
Aiming at the refresh rate and gray scale control problems encountered by the system of LED video display, this paper proposes a sub-area partition storage technology, and introduces its principle and implementation in detail. Through waveform simulation and engineering application, this method can well solve the problem of image flicker and large brightness loss in LED display control system, and its gray level and brightness control can be flexibly corrected.
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