Stm32f103zet6 is an embedded-microcontroller integrated circuit (IC). It is one of the STM32F1 series developed by ST. The core size is 32 bits, the speed is 72MHz, the program memory capacity is 256KB, and the program memory type is It is FLASH and the RAM capacity is 48K.
1. I = input, O = output, S = power, HiZ = high resistance
2. FT: Tolerance 5V
3. Some features are only supported on some models.
4. The PC13, PC14 and PC15 pins are powered by a power switch that can only sink a limited current (3mA). Therefore, these three pins have the following limitations as output pins: only one pin can be used as an output at the same time, and can only work in 2MHz mode as an output pin, the maximum driving load is 30pF, and cannot be used as a current source ( Such as driving LED).
5. These pins are in the main function state when the backup area is first powered up. After reset, the status of these pins is controlled by the Backup Area Register (these registers are not reset by the Master Reset System). For specific information on how to control these IO ports, refer to the battery backup area of ​​the STM32F10xxx Reference Manual and the relevant sections of the BKP register.
6. Unlike the LQFP64 package, there is no PC3 on the WLCSP package, but the VREF+ pin is provided.
7. This type of multiplexing can be configured by software to other pins (if the corresponding package model has this pin). For details, refer to the Multiplexing Function I/O section and Debugging Settings section of the STM32F10xxx Reference Manual.
8. Pins 5 and 6 of the LQFP64 package are configured by default to the OSC_IN and OSC_OUT function pins after a chip reset. Software can reset these two pins for PD0 and PD1 functions. However, for the LQFP100/BGA100 package and the LQFP144/BGA144 package, since PD0 and PD1 are inherent function pins, there is no need to re-image the software by software. For more details, please refer to the Multiplexing Function I/O chapter and Debugging Settings section of the STM32F10xxx Reference Manual.
9. LPFP64 packaged products, no FSMC function.
Annotation:
The ADC12_INx (x represents an integer between 4~9 or 14~15) appears in the pin name label in the table, indicating that this pin can be ADC1_INx or ADC2_INx. For example: ADC12_IN9 indicates that this pin can be configured as ADC1_IN9 or as ADC2_IN9.
Similarly, the ADC123_INx (x represents an integer between 0~3 or 10~13) appears in the pin name label in the table, indicating that this pin can be ADC1_INx or ADC2_INx or ADC3_INx.
TIM2_CH1_ETR in the multiplexing function corresponding to pin PA0 in the table indicates that the function can be configured as TIM2_TI1 or TIM2_ETR. Similarly, the name TIM2_CH1_ETR of the remapping multiplexing function corresponding to PA15 has the same meaning.
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