High-frequency inverter rear-stage circuit design

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The basic function of the latter circuit is to invert the high voltage DC power boosted from the previous stage into AC power. The full bridge structure is used the most from the structure.

The following is an example of the latter stage circuit of a single-phase sine wave inverter. Some of the circuits are as follows:

1. The effect of Miller capacitance on the safety of high voltage MOS tube and its solution

I remember that many netizens mentioned that the IR2110 promoted the full-bridge MOS to be very unstable. It is often inexplicably explosive. It is often good at low voltage test, and the bus voltage is increased when it is turned up. This is really a very headache. Let us first analyze the MOS junction GD junction capacitance, also known as the Miller capacitance on the upper and lower switches of the half bridge. The circuit for analysis is as follows:

In the figure, C1 and C2 are the GD junction capacitances of Q1 and Q2, respectively. The upper and lower waveforms on the left are the gate drive waveforms of Q1 and Q2, respectively. We start from the t1-t2 dead zone time. It can be seen from the figure that this time is the dead time, that is to say, the two pipes are not conducting during this time, and the midpoint voltage of the half bridge is half of the bus voltage. That is to say, C1, C2 charging is also half of the bus voltage. When the drive signal runs to time t2, the gate of Q1 becomes high level, Q1 starts to conduct, the potential of the midpoint of the half bridge rises sharply, C2 is charged by the bus voltage, and the charging current passes through the drive resistor Rg and the discharge circuit of the drive circuit. Q4, this charging current will generate a glitch voltage on the drive resistor Rg and the drive circuit discharge tube Q4. Please see the red vertical line at time t2 in the figure. If the magnitude of this glitch voltage exceeds the Q2 turn-on voltage Qth, the upper and lower tubes of the half bridge are common. Sometimes the upper and lower tubes are slightly common and do not necessarily explode, but the power tube will be heated. Observing the oscilloscope on the busbar will also see obvious interference burrs. Explosion is only possible when the common cause is serious. Another feature is that the higher the bus voltage, the higher the glitch voltage, and the more the fuse will be caused. Everyone knows the principle of this glitch voltage. I think it is very easy to solve this problem. There are three main solutions:

1) Use a gate active clamp circuit. It can be directly pulled down by a low-resistance MOS transistor at the gate of the MOS transistor to make it turn on in the dead zone;

2) using RC or RCD absorption circuits;

3) The gate plus negative voltage is turned off. This is the best way to translate the glitch voltage below the source level by level shifting, but the circuit is more complicated.

2. Problems needing attention in the IR2110 application

The IR2110 is an early half-bridge driver from IR. It has the advantages of low power consumption, simple circuit, and fast switching speed. It is widely used in the full-bridge driver of the inverter. For the IR2110 in the DIP16 package, the following points should be noted in the application of sine wave inverters:

1). The logic ground of pin 13 and the driving ground of pin 2 should be separated when routing. Generally, it should be connected to the negative terminal of 5V filter capacitor and then to the negative terminal of high voltage filter capacitor. The negative terminal of the filter capacitor of the 12-15V drive power supply, and the source of the MOS farther away from the two low-side high-voltage MOS transistors. As shown below:

2). In the sine wave inverter, because the carrier frequency is higher, the bus voltage is also higher, and the bootstrap diode uses a high frequency and high voltage diode. Since the carrier duty ratio is close to 100%, the capacity of the bootstrap capacitor is calculated according to the fundamental wave, and it is generally required to take 47-100uF, preferably a small high-frequency capacitor.

3. Calculation of sine wave inverter LC filter parameters

To accurately calculate the parameters of the sine wave inverter LC filter is indeed a cumbersome thing. Here I introduce a set of approximate simple calculation methods, which proved to be feasible in the actual test. My idea is that the filter inductor of SPWM is similar to the output filter inductor of a forward switching power supply, except that the pulse width of the SPWM is varied. The filtered voltage is a sine wave and not a DC voltage. If we calculate the maximum inductor ripple current in half a sinusoidal period, I think it is feasible. The following takes the output 1000W220V sine wave inverter as an example to calculate the parameters of the LC filter. First introduce the following physical quantities:

Udc: input the voltage of the inverter H bridge, the range of variation is about 320V-420V;
Uo: output voltage, 0-311V change, effective value is 220V;
D: The duty cycle of the SPWM carrier is constantly changing according to the sine law;
Fsw: switching frequency of SPWM, taking 20kHz as an example;
Io: output current, the peak current of the inductor is about 1.4 Io;
Ton: The conduction time of the switch tube is actually changed according to the sine law;
L: the amount of inductance required for the LC filter;
R: Load resistance of the inverter.

Then there are:
L=( Udc- Uo) Ton/(1.4 Io) (1)
D= Uo/ Udc (2)
Ton=D/ fsw= Uo/(Udc* fsw) ( 3)
Io=Uo/R (4)

Comprehensive (1), (3), (4) have:
L=(Udc- Uo)* Uo/(1.4 Io* Udc* fsw)=R(1-Uo/Udc)/(1.4 fsw)

For example, an inverter with an output power of 1000W assumes a minimum load of 15% of full load, R=220*220/(1000*15%)=323Ω

It can be seen from L= R(1-Uo/Udc)/(1.4 fsw) that the moment L0 of Uo=Udc does not require inductance; the smaller Uo is, the larger L is needed, we can take it as Uo=0.5 L=323*(1-0.5)/(1.4 *20000)=5.8 mH at Udc This value is calculated continuously according to the output current of 15% Io, so it is relatively large and can be corrected according to the minimum load of the inverter. For example, if the minimum load is 500W for half load, L is only 1.7 mH.

After determining the filter inductance, we can determine the filter capacitor C. The determination of the filter capacitor C is relatively easy. Basically, the filter cutoff frequency is calculated as 5-10 times of the fundamental wave. Its calculation formula is

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