Principle: When hardware I2C, SPI, try to use hardware operation, eliminating the tedious timing debugging of IO simulation. However, when the internal resources are not enough, the IO analog bus is used.
About short delays:
Whether to delay when simulating timing depends on the relative speed of the MCU and the device. For example, if the rate of 400K of I2C and the speed of MCU are no longer an order of magnitude, it is sure to adjust the timing by delay; but for SPI because of its high speed, even some are higher than the speed of the single-chip microcomputer, then There is no need to delay.
Whether the transceiver functions of the IO simulation should be combined into one:
Because SPI is full duplex, it can be separated, of course, it can be combined into one (no need to return value when sending, and the parameter is the data to be sent at the time of receiving, the return value is the value to be read)
About what is on the edge of the transition:
For example, in the chip manual, when sampling/locking on the rising edge (that is, the value must be stable after the leveling), the transmission and reception of a single bit should be performed between 0 and >1.
About clock polarity and clock phase:
The CPOL clock polarity only describes the level state of the bus when idle: CPOL = 1 indicates that the clock is flat when idle; otherwise it is low.
The CPOA clock phase illustrates sampling on the first transition edge, CPOA=0 indicating sampling on the first edge, otherwise on the second edge. 
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