Engineers share the experience of single-chip emc design, pay attention to a few seconds to become master

The operating frequency of the single-chip microcomputer should be designed according to the customer's needs to choose a lower operating frequency. First introduce the advantages of doing so: using a low crystal oscillator and bus frequency allows us to choose a smaller microcontroller to meet the timing requirements, so that the microcontroller The operating current can be made lower, and the most important is that the VDD to VSS current peak will be smaller.



Of course, we need to make a compromise here, because the customer's requirements may be compatible and platform-oriented (currently the development trend of automotive electronics is platform), choose a higher working frequency to be compatible with more platforms, and also facilitate future upgrades and Expand, so choose a lower acceptable working frequency.

Proper Output Drive Capability Given a load specification, rise and fall times, choosing the appropriate output rise time, minimizing the peak current of the output and internal drivers is one of the most important design considerations for reducing EMI. Mismatch in drive capability or uncontrolled output voltage change rate may result in impedance mismatch, faster switching edges, overshoot and undershoot of the output signal, or power and ground bounce noise.

Design the output driver of the single-chip microcomputer, first determine the load demanded by the module, the rise and fall time, the output current to be continued, according to the above information driving ability, control the voltage slew rate, only in this way can meet the module requirements and meet the EMC requirements. .

The following situations that the MCU needs to pay attention to when implementing EMC design:

First introduce the advantages of this: the use of low crystal oscillator and bus frequency allows us to choose a smaller microcontroller to meet the timing requirements, so that the operating current of the microcontroller can be lower, the most important is the peak current of VDD to VSS smaller.

Of course, we need to make a compromise here, because the customer's requirements may be compatible and platform-oriented (currently the development trend of automotive electronics is platform), choose a higher working frequency to be compatible with more platforms, and also facilitate future upgrades and Expand, so choose a lower acceptable working frequency.

Choosing the appropriate output rise time for a given load specification, rise and fall times, minimizing the peak current of the output and internal drivers is one of the most important design considerations for reducing EMI.

Mismatch in drive capability or uncontrolled output voltage change rate may result in impedance mismatch, faster switching edges, overshoot and undershoot of the output signal, or power and ground bounce noise.

First determine the load required by the module, the rise and fall time, the output current to be continued, according to the above information drive capability, control voltage slew rate, only in this way can meet the module requirements and meet EMC requirements.

A higher edge rate is produced when the drive capability is higher than the actual charge speed required by the load, which has two disadvantages:

1. The harmonic content of the signal is increased. 2. Together with the load capacitance and parasitic internal bonding lines, IC package, and PCB inductance, it will cause signal overshoot and undershoot.

Choosing the right di/dt switching characteristics can be achieved by carefully selecting the drive capability and controlling the voltage slew rate. The best option is to use a constant voltage slew rate output buffer that is independent of the load. The same pre-driver output voltage slew rate can be reduced (ie, the rise and fall times can be increased), but the corresponding propagation delay will increase, we need to control the total switching time).

The simplest of the programmable output ports is the parallel pair of drivers, their MOS Rdson can't, and the current capability can be different. We can choose different modes when testing and actually using them. In fact, current MCUs generally have at least two modes to choose from, and some can even have three (strong, medium, and weak).

Reducing the peak current of the synchronous switch, and di/dt, an important consideration is the ability to reduce the internal clock drive (in fact, the amplification factor, the punch-through current is very correlated). Reducing the current on the clock edge will significantly improve EMI. Of course, the disadvantage of this is that the average current of the microcontroller may increase due to the lengthening of the turn-on time of the clock and the load. Fast edges and relatively high peak currents, longer time edges and slower current pulses need to make a compromise.

This problem has actually been discussed before, and it will cause more interference when the gain is too large.

The punch-through current [overlap current, short-circuit current] is the current from the power supply to the ground when the PMOS and NMOS are simultaneously turned on during the switching process. The punch-through current directly affects the EMI and power consumption.

This content is actually inside the microcontroller, clock, bus and output drivers. The way to eliminate or reduce the shoot-through current is to turn off one FET and then turn on a FET. When the current is large, an additional pre-driver circuit or voltage slew rate is required.