As we all know, chip design is a very complicated and difficult big algorithm project. Throughout the current hardware market, there are a few manufacturers to control. In order to encourage new ventures and market competition, it is hoped that future college students will engage in hardware company startups to reduce development costs. The US research algorithm accelerators only need to focus on the algorithmic needs of specific applications.
The complexity of chip design and the rising cost have hindered the entry of hardware startups into the market. It is estimated that the cost of a new chip may be as high as 120 million US dollars depending on chip design, software and process, which not only adversely affects market competition, but also makes The hardware market is dominated by a few vendors.
According to reports, in order to encourage startups and market competition, the US Department of Defense's Advanced Research Projects Agency (DARPA) and Semiconductor Research CorporaTIon provided $27.5 million in research funding, hoping to popularize the design and manufacturing process and reduce the need to develop advanced computing systems. Cost, complexity. One of them is a program led by the Center for ApplicaTIons Driving Architectures, said Professor Valeria Bertacco, director of the center, who will develop an ecosystem of plug-and-play that encourages automation, robotics and machine learning. New computing ideas.
Bertacco expressed the hope that after five years, the newly graduated college students will be engaged in hardware company startups. As long as they focus on the algorithmic needs of specific applications, it is possible to create a computational hardware architecture or a reusable high-efficiency computational block calculus accelerator.
Bertacco said that instead of targeting the application itself, the design will focus on the underlying algorithms. The dedicated hardware design will be several orders of magnitude faster than the general-purpose chip. This specific-purpose hardware design has emerged, but it may take 10 years. A mature and efficient solution will emerge.
This approach can raise the level of abstraction beyond the depth of technology chip design issues such as timing and power optimization. From a hardware perspective, it is a matter of encapsulation, rather than a problem that needs to be solved from scratch. Newer semiconductor engineering and manufacturing developments, such as 2.5D technology using a germanium interposer to bond die with different process and operational characteristics, will help achieve this.
In the future, chip companies can produce off-the-shelf processor cores and accelerators. Anyone can buy an interposer and use the economies of scale of chip makers to design, saving hundreds of thousands or even millions of dollars.
Bertacco pointed out that for special areas where FPGAs are not available and CPU performance is not fully utilized, this algorithmic approach of offloading multiple accelerators to the tuning compiler is applicable. This idea blurs the boundaries between hardware and software, and hopes to think at the application level and consider how the compiler can automatically leverage a particular accelerator application to achieve the desired performance. Bertacco said that the future will be defined by heterogeneous processors, and existing accelerators defined by applications and compilers will work.
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